Plan 9 from Bell Labs’s /usr/web/sources/extra/9hist/mtx/clock.c

Copyright © 2021 Plan 9 Foundation.
Distributed under the MIT License.
Download the Plan 9 distribution.


## diffname mtx/clock.c 2001/1207
## diff -e /dev/null /n/emeliedump/2001/1207/sys/src/9/mtx/clock.c
0a
#include	"u.h"
#include	"../port/lib.h"
#include	"mem.h"
#include	"dat.h"
#include	"fns.h"
#include	"io.h"
#include	"ureg.h"

void
clockintr(Ureg *ureg)
{
	// this needs to be here for synchronizing mp clocks
	// see pc/mp.c's squidboy()
	fastticks(nil);

	if(m->flushmmu){
		if(up)
			flushmmu();
		m->flushmmu = 0;
	}

	portclock(ureg);
}

void
delay(int l)
{
	ulong i, j;

//	j = m->delayloop;
//	while(l-- > 0)
//		for(i=0; i < j; i++)
//			;
}

void
microdelay(int l)
{
	ulong i;

//	l *= m->delayloop;
//	l += 500;
//	l /= 1000;
//	if(l <= 0)
//		l = 1;
//	for(i = 0; i < l; i++)
//		;
}

vlong
fastticks(uvlong *hz)
{
	if(hz)
		*hz = HZ;
	return m->ticks;
}
.
## diffname mtx/clock.c 2001/1208
## diff -e /n/emeliedump/2001/1207/sys/src/9/mtx/clock.c /n/emeliedump/2001/1208/sys/src/9/mtx/clock.c
41,47c
return;
	l *= m->loopconst;
	l += 500;
	l /= 1000;
	if(l <= 0)
		l = 1;
	for(i = 0; i < l; i++)
		;
}

void
clockinit(void)
{
.
30,33c
	j = m->loopconst;
	while(l-- > 0)
		for(i=0; i < j; i++)
			;
.
22a
print("done portclock\n");
.
21a
print("portclock\n");
.
## diffname mtx/clock.c 2001/1212
## diff -e /n/emeliedump/2001/1208/sys/src/9/mtx/clock.c /n/emeliedump/2001/1212/sys/src/9/mtx/clock.c
43d
24d
22d
## diffname mtx/clock.c 2001/1218
## diff -e /n/emeliedump/2001/1212/sys/src/9/mtx/clock.c /n/emeliedump/2001/1218/sys/src/9/mtx/clock.c
48,52d
22a
if((m->ticks%HZ) == 0) print("tick! %d\n", m->ticks/HZ);
.
15a
	v = -getdec();
	if(v > clkreload/2){
		if(v > clkreload)
			m->ticks += v/clkreload;
		v = 0;
	}
	putdec(clkreload-v);

.
12,14c
	long v;
.
9a
clockinit(void)
{
//	delayloopinit();

//	clkreload = (m->clockgen/Timebase)/HZ-1;
	clkreload = (300000000/Timebase)/HZ-1;
	putdec(clkreload);
}

void
.
8a
static	ulong	clkreload;

// the following can be 4 or 16 depending on the clock multiplier
// see 15.3.3 in 860 manual
enum {
	Timebase = 16,	/* system clock cycles per time base cycle */
};

.
## diffname mtx/clock.c 2001/1219
## diff -e /n/emeliedump/2001/1218/sys/src/9/mtx/clock.c /n/emeliedump/2001/1219/sys/src/9/mtx/clock.c
47d
22,23c
	m->dechz = m->bushz/4;			/* true for all 604e */
	m->tbhz = m->dechz;				/* conjecture; manual says bugger all */

	delayloopinit();

	clkreload = m->dechz/HZ-1;		/* decremented at 1/4 bus clock speed */
.
20c
	/* XXX the hardcoding of these values is WRONG */
	m->cpuhz = 300000000;
	m->bushz = 66666666;
.
16a
	m->loopconst = 5000;
	v = getdec();
	delay(1000);
	v -= getdec();

	x = m->loopconst;
	x *= m->dechz;
	x /= v;
	m->loopconst = x;
}

.
11,15c
void
delayloopinit(void)
{
	ulong v;
	uvlong x;
.
## diffname mtx/clock.c 2002/0126
## diff -e /n/emeliedump/2001/1219/sys/src/9/mtx/clock.c /n/emeliedump/2002/0126/sys/src/9/mtx/clock.c
40c
	clkreload = m->dechz/HZ-1;
.
36c
	m->tbhz = m->dechz;				/* conjecture; manual doesn't say */
.
31c
	/* XXX this should not be hard coded! */
.
## diffname mtx/clock.c 2002/0410
## diff -e /n/emeliedump/2002/0126/sys/src/9/mtx/clock.c /n/emeliedump/2002/0410/sys/src/9/mtx/clock.c
91c
uvlong
.
63c
void
timerset(uvlong)
{
.
57,61c
	timerintr(ureg, 0);
}
.
## diffname mtx/clock.c 2002/0822
## diff -e /n/emeliedump/2002/0410/sys/src/9/mtx/clock.c /n/emeliedump/2002/0822/sys/src/9/mtx/clock.c
96a

/*  
 *  performance measurement ticks.  must be low overhead.
 *  doesn't have to count over a second.
 */
ulong
perfticks(void)
{
	return m->ticks;
}
.

Bell Labs OSI certified Powered by Plan 9

(Return to Plan 9 Home Page)

Copyright © 2021 Plan 9 Foundation. All Rights Reserved.
Comments to [email protected].