this is a plan 9 port to the Trimslice with tegra2 soc: dual-core,
dual-issue 1GHz Cortex-A9 system (v7a arch).

dram is 1GB at 0.
linux believes that u-boot runs in the bottom 4MB.
the l2 cache is a non-architectural bag nailed on the side.
mp arm systems have a generic interrupt controller; this one is gic v1(!).
vfp 3 floating-point is present.

section numbers (§) are in the tegra 2 tech. ref. man.
for a minimal cpu server, need these devices to work:
	clock signals §5 (leave to u-boot),
	pad mux + gpio crap §8, §11 and §18 (leave to u-boot),
☑	1 cpu §13,
☑	uart (16[45]50) §22,
☑	gic (gic.v1.pdf),
☑	clock §6—7,
☑	ether8169 via pcie §31.
then add these:
☑	2nd cpu (cortex.a9.mpcore.pdf),
☑	l2 cache (l2cache.pl310.pdf, errata),
☑	fpu (cortex.a9.fp.pdf),
☑	user profiling,
	kprof,
	in-line 64-bit arithmetic,
eventually might want:
	usb (e.g., for sata) §26,
	nor flash §17,
	video §29,
and the really horrid ones:
	nand flash §16,
	mmc §25.

physical memory map

0		1GB	ram

40000000 	256K	iram (audio/video memory)
50000000		cortex-a9 cpu regs, periphbase, intr distrib, memsel,
			l2 cache
54000000		graphics regs
58000000		gart (graphics window)
60000000	256MB	ppsb bus dev regs, including semas, intr ctlr, dma,
			arm7 cache, gpio, except. vects
70000000	256MB	apc bus regs, including uarts, nand, nor, spi, rtc

80000000	1GB	ahb extern mem, pcie for cpu only
90000000-97ffffff	pcie 0 mem(?)
a0000000-a7ffffff	pcie 0 prefetch mem, includes rtl8111dl ether(?)
a0020000		ether region 4
a0024000		ether region 2

c0000000	256MB	ahb bus			virtual b0000000
c3000000-c80007ff 81MB	ide, usb, sata, mmc
d0000000	256MB	nor flash		virtual 40000000
f000f000	4K	mmu tlb
fff00000	48K	irom boot code
ffff0000	64K	high vectors

use 0xc0000000 as KZERO.